Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language that facilitates hardware design and verification. It is built on top of the Scala programming language, leveraging its expressiveness and functional programming capabilities to enable designers to create sophisticated hardware designs and testbenches with ease. Chisel is primarily used in the development of digital circuits, particularly in the realm of FPGA and ASIC design.
Chisel was developed as a research project at the University of California, Berkeley, under the auspices of the Berkeley Architecture Research group. The motivation behind its creation was to provide a more productive and efficient means of designing hardware compared to traditional Hardware Description Languages (HDLs) like Verilog or VHDL. By embedding hardware design within a high-level programming language, Chisel aimed to offer better abstraction, higher-level constructs, and code reuse.
Since its inception, Chisel has gained popularity within academic and industrial settings. The language has evolved with contributions from numerous developers, leading to improvements in its features, libraries, and usability. Its integration with Scala has allowed designers to leverage powerful features like functional programming, type safety, and advanced collection libraries. Chisel is now widely used in modern hardware development projects, ranging from academic research to commercial products.
Chisel draws inspiration from HDLs such as Verilog and VHDL, borrowing their core concepts while enhancing them with programming paradigms from Scala. It also relates closely to other hardware construction frameworks like SpinalHDL, which similarly focus on productivity and expressiveness. Chisel designs can be converted into Verilog, enabling the use of existing synthesis tools and workflows.
Chisel provides an embedded Domain-Specific Language (DSL) within Scala, allowing hardware designers to utilize Scala's syntax for hardware description. For example, defining a simple 2-input multiplexer can be expressed as:
class SimpleMux extends Module {
val io = IO(new Bundle {
val a = Input(Bool())
val b = Input(Bool())
val sel = Input(Bool())
val out = Output(Bool())
})
io.out := Mux(io.sel, io.b, io.a)
}
Chisel supports a variety of types and allows designers to specify bit widths explicitly, providing better control over hardware resource utilization. For instance:
val myWire = Wire(UInt(8.W)) // 8-bit unsigned integer
The language offers abstractions for common hardware components. For example, to create a simple register:
val reg = RegInit(0.U(8.W)) // 8-bit register initialized to 0
Chisel allows the creation of parameterized modules, enabling reusable designs with different configurations:
class ParamModule(val size: Int) extends Module {
val io = IO(new Bundle {
val input = Input(UInt(size.W))
val output = Output(UInt(size.W))
})
io.output := io.input + 1.U
}
Chisel supports conditional expressions to facilitate complex hardware logic:
val result = Mux(condition, trueValue, falseValue) // Multiplexer
Construct modular hardware components using higher-order functions to generate hardware configurations:
def makeAdder(n: Int) = new Module {
val io = IO(new Bundle {
val a = Input(UInt(n.W))
val b = Input(UInt(n.W))
val sum = Output(UInt(n.W))
})
io.sum := io.a + io.b
}
Chisel allows the use of Scala collection utilities to manipulate hardware elements effectively:
val wires = VecInit(Seq.fill(4)(Wire(UInt(8.W)))) // Create a vector of 4 wires
Sequential logic is expressed easily using Chisel's dedicated constructs, like registers:
when(condition) {
reg := newValue
} .otherwise {
reg := oldValue
}
Chisel integrates with ScalaTest, enabling developers to write tests for their hardware designs naturally:
class MyModuleTester extends PeekPokeTester(new MyModule) {
poke(dut.a, 1)
poke(dut.b, 0)
expect(dut.out, 1)
}
Chisel supports method chaining, allowing concise and readable definitions of complex hardware circuits:
val result = (a + b).asUInt + c
Chisel can be developed using any IDE that supports Scala, such as IntelliJ IDEA with the Scala plugin. Additionally, sbt (Scala Build Tool) is commonly used to manage projects and dependencies, as well as to compile Chisel projects into Verilog code.
To create a Chisel project, you can set up a standard sbt project structure. A simple build.sbt file might look like this:
name := "MyChiselProject"
version := "0.1"
scalaVersion := "2.12.10"
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4"
To build, you would run sbt run from the command line and the output Verilog files will be generated in the target directory.
Chisel is predominantly used in digital hardware design and verification. It finds applications in areas such as:
Chisel stands apart from traditional HDLs like Verilog and VHDL by offering features found in high-level programming languages, such as functional programming, type safety, and higher-level abstractions.
Compared to other languages:
For translating Chisel to other hardware description languages, tools like the Chisel compiler can generate Verilog directly from Chisel source code. There are no widely known source-to-source translation tools that convert Chisel directly to another HDL, but the generated Verilog can be manually adapted if required.
Currently, the most recognized tool is the Chisel toolchain itself, which allows users to compile Chisel designs into synthesizable Verilog code. There are also efforts to integrate Chisel with other hardware frameworks through various libraries and tools, fostering collaboration and interoperability among different hardware design methodologies.